RTL Lead (Hea Job/ 260)

About Sanlayan
Sanlayan Technologies Pvt. Ltd. is an Indian defence and aerospace electronics company focused on building indigenous, mission-critical systems for land, air, sea, and space applications. Founded by IIT/IIM alumni, Sanlayan is accelerating India’s self-reliance in strategic technologies through advanced R&D, embedded systems, and full-spectrum product development. With the recent acquisition of Dexcel Electronics, the company has strengthened its capabilities in avionics, radar electronics, and embedded solutions. Sanlayan is rapidly growing and actively hiring top talent to work on high-impact national projects.
● Job Title: RTL Engineer
● Location: Bangalore, India
Key Responsibilities:
1. FPGA Design and Development:
● Develop RTL code for FPGAs using VHDL, Verilog, or SystemVerilog.
● Design and implement digital signal processing (DSP), high-speed interfaces, and control logic for aerospace systems.
● Optimize FPGA designs for performance, power consumption, and resource utilization.
● Develop and implement FPGA designs targeting Xilinx RFSoC platforms (e.g., Zynq UltraScale+ RFSoC).
● Configure RF data converters (ADC/DAC) and optimize them for high speed, low-latency performance.
● Implement digital signal processing algorithms, such as filtering, modulation, demodulation, and beamforming, in the FPGA fabric.
2. Signal Processing and RF Performance Optimization:
● Develop and optimize FPGA-based RF signal processing pipelines for applications like radar, electronic warfare, 5G, and satellite communications.
● Analyze RF performance metrics such as noise figure, spurious-free dynamic range (SFDR), and phase noise to meet system requirements.
3. System Integration:
● Collaborate with hardware, software, and systems engineers to integrate FPGA designs into larger systems.
● Implement and test high-speed protocols like PCIe, Ethernet, SPI, or UART.
4. Verification and Testing:
● Develop simulation testbenches for functional verification using tools like ModelSim, QuestaSim, or XSIM.
● Perform hardware-in-the-loop (HIL) testing and debug FPGA designs using lab equipment such as oscilloscopes, logic analyzers, and protocol analyzers.
5. Standards and Compliance:
● Ensure FPGA designs comply with aerospace and defence standards (e.g., DO-254, MIL-STD-810, or equivalent).
● Maintain thorough documentation, including requirements, design specifications, and verification results.
6. Continuous Improvement:
● Stay updated on the latest FPGA technologies and tools from vendors like Xilinx, Intel (Altera), or Microchip (Microsemi).
● Contribute to the development of design methodologies, reusable IP blocks, and best practices.
Requirements:
Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
Experience:
● Minimum 3-4 years of hands-on experience in FPGA design and development, preferably in aerospace or defence applications.
● Proven experience with FPGA tools (Vivado, Quartus, Libero) and simulation tools.
Skills:
● Good knowledge of RTL design, synthesis, and timing analysis.
● Familiarity with FPGA architectures from Xilinx, Intel, or Microchip.
● Proficient in implementing DSP algorithms and hardware accelerators in FPGA.
● Good in coding languages (VHDL, Verilog, SystemVerilog).
● Familiarity with safety-critical development standards like DO-254.
● Understanding of aerospace-specific data buses such as ARINC 429, MIL-STD 1553,
● Experience with FPGA simulation tools (ModelSim, QuestaSim, etc.).
● Proficiency in timing analysis and static timing tools.
● Knowledge of version control systems (Git, SVN).
● Debugging FPGA designs using lab tools and addressing complex timing and resource constraints.
● Strong understanding of RF concepts, including modulation schemes, filtering, and spectral analysis.
● Experience with DSP algorithms for RF systems, such as FFTs, FIR/IIR filters, and digital down/up converters (DDC/DUC)
● Experience with high-speed serial interfaces like JESD204B/C, PCIe, and Gigabit Ethernet.
● Knowledge of DDR memory interfaces and AXI interconnects.