Lead Engineer (FPGA, DDR) (Hea Job/ 262)

Skill Set Requirements

Key requirements

Primary skill requirements of all engineers will be

• Exceptional Digital fundamentals
• Hands on experience in System Design with FPGA devices with relevant FPGA EDA tools
• Experience in designing and implementing FPGA based solution in Microchip or Xilinx or Altera FPGAs
• Write high quality code in Verilog/System Verilog, VHDL and C code for embedded processors.  Maintain existing code.
• Developing testbenches using Verilog/System Verilog and verifying validation designs in simulation environment using BFM/VIP
• Experience in using Synthesis, Placement constraints
• STA constraint definition and Timing closure for high speed designs
• Validation of FPGA based implementation on HW board
• Experience in writing embedded FW programs in C/C++
• Strong Lab debug experience and enthusiasm & patience to solve systems level hardware issues using Lab equipment, Embedded debuggers and RTL debuggers
• Be conversant with on-chip debug tools
• Experienced with scripting tcl/perl
• Exposure to Version management systems, GitHub, SVN
• Excellent verbal and written communication skills in English
• Strong technical background in silicon validation, failure analysis and debug
• Understand hardware architectures, use models and system level design implementations required to utilize the silicon features. 

Skill needs based on experience

• Lead Engineer [Serdes/DDR/SOC/Configuration Security] 6-8 yrs
  • Strong hands-on FPGA Silicon validation experience
  • Must have protocol expertise in one or more of PCIe-Gen4/5, DDR-4/5, Ethernet, Processor based subsystem.
  • Knowledge of RISC-V processor is a plus
  • Proven track record of planning, executing and handling complex FPGA System Project using Processor based test cases
  • Be responsible for self and team level deliverables of assigned Use Model and Use Cases. Manage work assignments for a group of junior and senior engineers.
  • Train and mentor junior team members and bring them upto speed on the validation activity
  • Track and follow up on dependencies for design creation, embedded software drivers, IP, HW etc.
  • Support and provide guidance to junior team members in debugging issues
  • [Serdes] Excellent knowledge of PMA/PCS architecture, DFE, CTLE. Experience with compliance testing, interop testing and usage of Ethernet traffic testers, PCIe exerciser, network traffic testers etc.
  • [DDR] Excellent knowledge of the DDR memory interface training, initialization and controller validation. Use of debug equipment such as logic analyzers. Performance and stress testing of the interface for robustness.
  • [SOC] Excellent knowledge of processor subsystem validation, bus architecture, application development, NOC, vector processor, peripheral interfaces, boot modes, trace debug. Performance and bandwidth testing.
  • [Configuration & Security] Excellent knowledge of Embedded System development and debug on RISC-V/ARM, PQC, PUF, Crypto, Firmware, SI Characterization, Good at Mathematical Analysis, Expert in SPI/QSPI/Octal SPI, Exposure to Microchip FPGAs & flow